BSX320误码率测试仪

主要性能指标

• 高达 32 Gb/s 的码型发生和误码分析功能

• 选配内置 4 阶发射机均衡功能,支持交互式链路训练

• 面向协议和面向位的多链码型定序技术,增强型码型/序列编辑器

• 激励响应反馈,用户自定义检测器码型匹配

• 已获的误码定位分析技术（Error Location Analysis™ ）,超越BER测量,分析关联度和确定性错误码型,深入了解误码根源

• 选配前向纠错分析技术,根据测得误码位置码型仿真FEC后误码率

• 集成眼图和 BER 关联功能,包括模板测试、抖动峰值、BER轮廓

• 选配抖动分离及定位 (Jitter Map) 系统,提供丰富的抖动解析 – 支持长码型（如 PRBS-31）

主要特点

• 为接收机压力测试、调试和一致性测试提供单一解决方案

• 测试第三代和第四代标准,包括 PCIe、SAS 和 USB3.1 及各种自主开发的标准

• 超过 16 Gb/s 的 DUT 握手功能,满足环回发起和自适应链路训练的接收机测试要求,支持 PCIe 等主要标准

• 协议识别码型发生和误码检测,支持灵活的激励响应编程能力,调试握手问题。

• 前向纠错(FEC)仿真选项,可以测量纠错前和纠错后BER,支持常用的Reed-Solomon FEC代码。

• 为各种主要标准提供了校准和测试自动化软件

应用

• 设计验证,包括信号完整性、抖动和时序分析

• 测试高速串行系统、复杂设计的性能

• 设计/验证高速 I/O 组件和系统,包括 DUT 握手

• 信号完整性分析 – 模板测试、峰值抖动、BER轮廓、抖动分离及定位（Jitter Map)和前向纠错仿真

智能内存排序

由于面向位的内存排序模式和协议识别内存排序模式,另外由于能够根据用户自定义检测器码型匹配情况推进排序器,BSX 系列允许用户创建自己的基于协议的码型和握手序列。

Key performance indicators

Up to 32 Gb/s code type generation and error code analysis function

Optional built-in 4 - stage transmitter balance function, support interactive link training

Protocol - and bit - oriented multi - chain code - type sequencing technology, enhanced code - type/sequence editor

Excitation response feedback, user - defined detector pattern matching

Error positioning Analysis technology patents (Error Location Analysis ™), beyond the BER measurement, Analysis of correlation and deterministic Error type, understａnd Error source

Forward error correction analysis technology is selected to simulate the backward error rate of FEC according to the measured error code position code type

Integration of eye map and BER association function, including template testing, jitter peak, BER contour

Optional Jitter Map system to provide rich Jitter resolution -- support for long code types (e.g.Prbs-31)

The main features

Provides a single solution for receiver pressure testing, debugging and conformance testing

Testing third and fourth generation standards, including PCIe, SAS and USB3.1, and various self-developed standards

The DUT handshake function exceeding 16 Gb/s meets the receiver test requirements of loopback initiation and adaptive link training, and supports PCIe and other major standards

Protocol identification code type occurrence and error detection, support flexible excitation response programming ability, debugging handshake problem.

Forward error correction (FEC) simulation option, can measure before and after error correction BER, support common reed-solomon FEC code.

Provides calibration and test automation software for major standards

application

Design verification, including signal integrity, jitter and timing analysis

Test the performance of high-speed serial system and complex design

Design/verify high speed I/O components and systems, including the DUT handshake

Signal integrity analysis -- template test, peak Jitter, BER contour, Jitter Map and forward error correction simulation

Intelligent memory sort

The BSX series allows users to create their own protocol based code types and handshake sequences, due to the bit-oriented memory sorting pattern and protocol recognition memory sorting pattern, and the ability to advance the sorter based on user-defined detector code type matches.